QThink Design Services Adopts Magma's Titan and Talus to Implement Next-Generation Mixed Signal Designs

Bangalore : Magma® Design Automation Inc., a provider of chip design software, announced today that QThink® Design Services has added Titan™ Chip Finishing to its Talus®-based design flow to implement next-generation digital and mixed-signal designs. By leveraging Titan’s tight integration with the Talus IC implementation system, Qthink can automate what are traditionally manual, repetitive and time-consuming steps in the chip finishing process, allowing them to provide their customers with shorter development cycles and reduced development costs.

“With third-party chip finishing, an inordinate amount of time is spent performing manual chip integration tasks such as top-level routing, connecting to the package routing layers, implementing last minute ECOs and adding manufacturing data,” said Urban Jangren, vice president of Engineering at QThink. “Titan is significantly faster and provides higher capacity than any other chip finishing tool we’ve used. It has turned several day’s of manual work into a scripted flow executed in minutes!”

“The Magma software offers the highest level of integration and automation, allowing designers to deliver ICs with better quality of results with less effort and in less time,” said Suk Lee, general manager of Magma’s Custom Design Business Unit. “QThink’s decision to use the Magma software is a strong endorsement of its ability to improve designer productivity.”

Titan: Lightning-Fast, Automated Chip Finishing and Live Integration with Digital Implementation

In traditional flows, chip finishing -- the point at which the digital and analog blocks of a design are integrated together -- is a time-consuming and manual task. Titan Chip Finishing provides complete and automated chip finishing capabilities. This fast, high-capacity system integrates mixed-signal layout with the Talus place-and-route capabilities. Titan Chip Finishing can manipulate the largest designs with ease, automates analog and special-net routing through an efficient constraints-based approach and makes all mixed-signal layout changes immediately available for physical and timing verification sign-off analysis through a live interface with Talus, Quartz™ DRC and Quartz LVS. Titan Chip Finishing can implement late engineering change orders (ECOs) that affect both analog and standard-cell components without significantly delaying the schedule.