Certess Announces the First C-Level Functional Qualification Tool

ANSI C Support Enables Earlier and Dramatically Faster Qualification of Verification Environment

CAMPBELL, Calif : Building on its leadership in functional qualification, Certess™, Inc., today announced Certitude™ -C, the next generation of its functional qualification software product for companies developing SoCs or integrating intellectual property (IP) blocks using C. Certitude-C adds support for ANSI C to the capabilities of the original product, allowing functional qualification of both reference models and high-level representations of designs written in C. This results in qualification of the verification environment earlier and more efficiently than was previously possible. Identifying bugs and other issues at the C level decreases both the time and cost of eliminating them, resulting in faster design times and lower overall costs. Certitude-C is the industry’s first design tool to offer C-level functional qualification.

Code coverage is available for C-written reference models, but it only determines whether the code has been executed. Similarly, in the design verification flow for high-level or architectural synthesis, equivalency checking can be used to ascertain if the RTL (Register Transfer Level) code generated is the same as the C model, but not whether bugs could exist in the model and remain undetected by either C or RTL verification.

Certitude-C functional qualification can help rapidly find and correct weaknesses in functional verification, allowing functional bugs in ANSI C models to be found, and it can be used to objectively measure the quality of the verification of IP blocks written in C for high-level synthesis. This complements the qualification using RTL code, which is only available later in the design flow and runs more slowly. The availability of functional qualification for C models that can be compiled and run directly on a computer dramatically boosts the ability of the designer and verification engineer to ensure that the desired functionality has been properly verified.

“The increasing complexity of designs means that there is an accelerating move toward higher levels of abstraction for hardware design, because higher level models are much smaller, run much faster and are easier to understand,” said Michel Courtoy, President and CEO of Certess. “Certitude-C provides designers who are designing in C and using high-level synthesis with a way to functionally qualify their models, and to ensure that their verification environment can actually identify bugs, before RTL code is generated. This saves them both time and money, and ensures a better quality design.”

Certitude-C is currently being integrated for reference model qualification at STMicroelectronics, and is used in conjunction with the leading high-level synthesis flows, such as Synfora’s PICO Extreme™ and Mentor Graphics’ Catapult® C Synthesis. It has demonstrated significant benefits in terms of earlier and faster functional qualification.

“Certess’ introduction of Certitude-C is a clear demonstration of the increasingly robust ANSI C design and verification flows,” said Shawn McCloud, Product Line Director, High Level Synthesis, Mentor Graphics. “With Certitude-C, design teams can achieve a high degree of functional coverage of their ANSI-C models before synthesizing with Mentor’s market leading Catapult C Synthesis providing a risk free flow which slashes months off their time to fully verified RTL.”

“Certitude-C and PICO Extreme is a compelling combination already proven by leading customers. Designers benefit from leveraging C to verify complex applications quickly and efficiently and use PICO to build a complete application from a single C program which is delivering better results faster and combines significant productivity gains in implementation and verification,” said Simon Napper, CEO of Synfora Inc. “The availability of Certitude-C combined with PICO-generated complete verification environment allows designers to be even more effective at verifying complex IP at the C level and further complete and leverage the high-level synthesis flows deployed by most advanced customers.”