Jasper Design Automation Provides First North American Demonstrations of ActiveDesignTM With Behavioral IndexingTM at DVCon 2009

DVCon Reserved for Exclusive Unveiling of New Technology and Services From Jasper
DVCon 2009
Booth #902

MOUNTAIN VIEW, Calif. - Jasper Design Automation, provider of advanced formal technology solutions, today announced that at DVCon 2009, it will demonstrate its expanding portfolio of design, verification and design reuse solutions, built upon patented formal and visualization technology. DVCon attendees are invited to visit Jasper in booth # 902, and meet with Jasper's formal technology experts to view the first public North American demonstrations of the company's recently announced ActiveDesign™ with Behavioral Indexing™. This breakthrough solution enables efficient design reuse, and drives higher RTL design quality and greater designer productivity. In addition, there will be an exclusive unveiling of innovative new technology and services from Jasper.

With ActiveDesign, IC design groups, CAD teams responsible for design flows and leveraging internal IP, commercial IP vendors, and design services companies now have a much-needed solution for efficient design reuse - a growing electronics industry imperative - as well as for increasing baseline design quality. ActiveDesign uses formal analysis, coupled with Jasper's patented visualization and Behavioral Indexing technologies, to iteratively extract, capture, index and store relevant design behaviors, along with the RTL, in a dynamic, executable database referred to as Activated IP™. Activated IP is a design database optimized for complex yet flexible behavior-based analysis and automatic regressions. Designers can explore design behaviors via waveforms automatically from the RTL itself (without a testbench) and accelerate design comprehension. ActiveDesign delivers dramatic benefits in efficient design reuse, higher baseline RTL quality, greater designer productivity, verification time reduction, accelerated knowledge transfer and improved design maintenance.

The latest releases of JasperGold® Verification System and JasperGold® Express will also be demonstrated at DVCon. These production-proven formal verification solutions are used by logic designers, verification engineers and silicon bring-up teams for a wide spectrum of applications: architectural validation, RTL design, exploration and debug, verification, low power verification, post-silicon validation and debug.

Panel: "Mixing Formal Analysis with Simulation: Why, When, Where, and How?"

Be sure to attend DVCon's Thursday panel entitled, "Mixing Formal Analysis with Simulation: Why, When, Where, and How?" Lawrence Loh, Jasper's Director of Worldwide Applications Engineering, will provide a perspective on combined formal and simulation methodologies. This panel will take place in the Donner/Siskiyou Ballroom on Thursday, February 26th from 3:30 pm to 5:00 pm. For further details about this panel, please visit the DVCon website or go to: http://www.dvcon.com/html/panel2.html.