Lattice Announces Updates and Enhancements to Its FPGA Design Tool Suite

HILLSBORO, OR - Lattice Semiconductor Corporation today announced the immediate availability of Service Pack 1 for Version 8.0 of its ispLEVER® FPGA design tool suite. Service Pack 1 is an important update for users of LatticeECP3™ FPGA devices.

"Service Pack 1 enhances and extends design support of the LatticeECP3 family to enable users to achieve low cost, low power design goals. More specifically, this important update allows users of the ECP3-150EA device to design with even greater confidence that the board-level behavior of their design, such as power and timing, will match what the tools report," said Mike Kendrick, Lattice's Manager of Software Product Planning. "SP1 also further boosts DSP application performance in the LatticeECP3 devices."

Updated Support for the LatticeECP3 FPGA Family

Service Pack 1 updates the device values to production characterized silicon for the LatticeECP3-150EA device. With SP1, static timing analysis, timing simulation and power calculation will report results that even more accurately reflect the behavior of the actual production device. Moreover, PCS/ SERDES calibration settings used for the supported IO protocols have been tuned to provide more robust behavior. HDL generation of generic DDR interfaces from the IPexpress™ tool, first introduced in ispLEVER 8.0, has been enhanced to include two additional interfaces, resulting in more design and implementation flexibility. There is also additional flexibility in the choice of pins for generic DDR interfaces. Synplify Pro® synthesis has added several enhancements, allowing higher performance and lower utilization in DSP-centric applications by further exploiting the unique sysDSP™ Block cascading capability.

About the ispLEVER Design Tool Suite
The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more. The ispLEVER tool suite is available for download, or on DVD for Windows, UNIX or Linux platforms. Synopsys' Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec's Active-HDL Lattice Edition simulator is included for Windows.

Third Party Tool Support
In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, which are included in the ispLEVER tool suite, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support the latest Lattice devices, including the LatticeECP3 family.

Pricing and Availability
The ispLEVER 8.0 Service Pack 1 tool suite for Windows, UNIX and Linux users is available immediately without charge for customers with active design tool maintenance contracts. Pricing for the full ispLEVER design tool suite starts at $1,295 for the Windows version.