Simulation of assertions accelerated thanks to SLED SDG

Grenoble, France: Assertion-Based Verification (ABV) has been promoted for a number of years and the use of assertions is spreading among verification teams. However, despite the fact that assertions help verify that a circuit behaves as specified, some designers can be reluctant to use them as the mixing of a language like PSL within circuit descriptions in Verilog or VHDL can excessively slow down the overall simulation.

SLED SDG is the solution of choice for designers needing to benefit from the advantages of PSL assertions, but not willing the reduction of simulation speed. Actually, SLED SDG automatically generates synthesizable VHDL or Verilog modules from PSL assertions. When using these generated modules instead of assertions, designers get around the inadequate support of PSL by logic simulators and benefit from their specific RTL optimizations to accelerate simulation with assertions.

SLED SDG easily fits into existing design flows as it is accessible in batch mode from the command line or by using scripting languages.

Moreover, SLED SDG extends Assertion-Based Verification to the hardware world as the generated VHDL or Verilog modules are synthesizable: the RTL checkers can be embedded into FPGA or testchip to monitor assertions during real-time execution of the circuit. Such on-line detectors can be maintained within a System-on-Chip targeting security or critical applications and they allow putting in place corrective actions as soon as signals or alerts are triggered.